Monday, April 13th 2026
Intel Core Ultra "Nova Lake-S" Desktop Core Configurations Surface
CPU core configurations of Intel's next-generation Core Ultra Series 4 "Nova Lake-S" desktop processors were leaked to the web by VideoCardz. These processors will remain disaggregated, tile-based chips, much like current Core Ultra Series 2 "Arrow Lake-S," but Intel will probably rearrange components around the various tiles. These chips will also introduce low-power island E-cores (LPE-cores) to the socketed desktop platform. The new processors will be designed for Socket LGA1954, which will be significantly different from the current LGA1851, while retaining cooler compatibility.
Intel intends LGA1954 to have longevity spanning several processor generations lasting till the end of the decade. The Core Ultra Series 4 will span a wide range of price-points, starting with Core Ultra 3, having the least core-count, going all the way up to Core Ultra 9 (probably X9). Perhaps the most interesting bit of news is the introduction of dual-die processors. These are SKUs with two Compute tiles connected to the SoC tile. This allows Intel to achieve extremely high CPU core counts. Since this is essentially the same approach to high core counts as AMD, both Compute tiles have equal access to memory and PCIe.
The series begins with the first kind of SKUs, probably Ultra 3, with a 4P+0E+4LPE cores, so that's four "Coyote Cove" performance cores, no E-cores within the main CPU complex, but four "Arctic Wolf" low-power island E-cores in the SoC tile. The total core-count is therefore 8.
The second kind of SKUs come with a 4P+8E+4LPE configuration: four "Coyote Cove" performance cores, eight "Arctic Wolf" E-cores within the compute complex, sharing L3 cache with the P-cores; and four "Arctic Wolf" low-power island E-cores, for a total core-count of 16.
The third kind sees a steep rise in core counts, now up to 8P+16E+4LPE; that's eight "Coyote Cove" performance cores, sixteen "Arctic Wolf" E-cores within the main CPU complex, sharing L3 cache with the P-cores, and those four low-power island E-cores, pushing core-count to 28.
Here's where things get interesting. Intel is introducing the concept of bLLC, or "big last-level cache," its answer to AMD's 3D V-Cache technology. It sees the introduction of an in-package cache die that augments the on-die L3 cache that's part of the CPU complex. There will be one kind of SKUs with 8P+16E+4LPE core configuration with this bLLC. Intel might introduce a new brand extension to denote this SKU separately from the regular 8P+16E+4LPE SKUs. The recent introduction of "Core Ultra X9" and "Core Ultra X7" with "Panther Lake" mobile processors could provide some clue.
Perhaps the most astounding development is the fabled extreme core-count desktop processor featuring two Compute tiles with bLLC dies on top. This chip has an astounding 16P+32E+4LPE core-configuration, and Intel could create SKUs that max-out this core-count, or come up with cut-down configurations such as 16P+24E+4LPE.
All SKUs will come with certain common on-die components and I/O. All chips will feature a next-generation NPU6 device that meets Microsoft Copilot+ local acceleration hardware requirements. Every SKU will come with preparation for two Thunderbolt 5 or USB4 V2 ports (80 Gbps bidirectional or 120+40 Gbps asymmetric), however, implementation of these ports will depend on motherboard vendors, based on chipset SKU. All chips will feature a 2-channel DDR5 memory interface, and Intel is expected to increase the native memory speeds, maximum memory capacity, and offer native support for 4-rank DDR5 DIMMs. The integrated graphics solution is based on the Xe3 "Celestial" graphics architecture, with no more than 2 Xe3 cores, which should match or exceed graphics performance of the current "Alchemist" based iGPU powering "Arrow Lake-S."
Source:
VideoCardz
Intel intends LGA1954 to have longevity spanning several processor generations lasting till the end of the decade. The Core Ultra Series 4 will span a wide range of price-points, starting with Core Ultra 3, having the least core-count, going all the way up to Core Ultra 9 (probably X9). Perhaps the most interesting bit of news is the introduction of dual-die processors. These are SKUs with two Compute tiles connected to the SoC tile. This allows Intel to achieve extremely high CPU core counts. Since this is essentially the same approach to high core counts as AMD, both Compute tiles have equal access to memory and PCIe.
The second kind of SKUs come with a 4P+8E+4LPE configuration: four "Coyote Cove" performance cores, eight "Arctic Wolf" E-cores within the compute complex, sharing L3 cache with the P-cores; and four "Arctic Wolf" low-power island E-cores, for a total core-count of 16.
The third kind sees a steep rise in core counts, now up to 8P+16E+4LPE; that's eight "Coyote Cove" performance cores, sixteen "Arctic Wolf" E-cores within the main CPU complex, sharing L3 cache with the P-cores, and those four low-power island E-cores, pushing core-count to 28.
Here's where things get interesting. Intel is introducing the concept of bLLC, or "big last-level cache," its answer to AMD's 3D V-Cache technology. It sees the introduction of an in-package cache die that augments the on-die L3 cache that's part of the CPU complex. There will be one kind of SKUs with 8P+16E+4LPE core configuration with this bLLC. Intel might introduce a new brand extension to denote this SKU separately from the regular 8P+16E+4LPE SKUs. The recent introduction of "Core Ultra X9" and "Core Ultra X7" with "Panther Lake" mobile processors could provide some clue.
Perhaps the most astounding development is the fabled extreme core-count desktop processor featuring two Compute tiles with bLLC dies on top. This chip has an astounding 16P+32E+4LPE core-configuration, and Intel could create SKUs that max-out this core-count, or come up with cut-down configurations such as 16P+24E+4LPE.
All SKUs will come with certain common on-die components and I/O. All chips will feature a next-generation NPU6 device that meets Microsoft Copilot+ local acceleration hardware requirements. Every SKU will come with preparation for two Thunderbolt 5 or USB4 V2 ports (80 Gbps bidirectional or 120+40 Gbps asymmetric), however, implementation of these ports will depend on motherboard vendors, based on chipset SKU. All chips will feature a 2-channel DDR5 memory interface, and Intel is expected to increase the native memory speeds, maximum memory capacity, and offer native support for 4-rank DDR5 DIMMs. The integrated graphics solution is based on the Xe3 "Celestial" graphics architecture, with no more than 2 Xe3 cores, which should match or exceed graphics performance of the current "Alchemist" based iGPU powering "Arrow Lake-S."
109 Comments on Intel Core Ultra "Nova Lake-S" Desktop Core Configurations Surface
Realistically, you can expect a TDP of 350–500 W.
4P+8E makes sense as it's half of one compute tile. Less than this seems ridiculous for a socket with two levers for the ILM, I mean really if you're that poor buy something else.
6P+12E also makes sense as it's in-between half tile and full tile. Intel seems to think otherwise, of course they know better the proof for that is what they did up until now. :rolleyes:
8P+16E w bLLC makes sense as non-bLLC full tile would be too close to be relevant. Not only that the full tile needs something extra to have a sizeable gain over the 6P+12E.
6P+12E is 50% core increase over 4P+8E thus respectable gain, whereas 8P+16E is 33% core increase over 6P+12E thus smaller gain, but with bLLC it can be big enough to justify the extra cost that bLLC will incur to the SKU.
Next we have two compute tiles.
12P+24E w bLLC makes sense as it's in-between one full tile and two full tiles. Each tile having 6P might give it a slight limp similar to the 9900X in certain scenarios.
16P+32E w bLLC obviously needs to happen as not maximizing the socket is plain stupid. I don't know if the extra tile can help this SKU against the one full tile w bLLC in gaming (strictly the cores not frequency difference etc.). Perhaps sometimes which would imply that game scales past the full tile core config. We'll see, this monster is obviously meant to win the MT crown for Intel.AMD has TDP and PPT. Intel has PBP and MTP.
270K and 285K have 125 W PBP and 250W MTP.
If the two compute tile Nova Lake SKU has 175 W PBP the MTP will be at least 300 W, maybe 350 W.
The cheapest bLLC SKU would be interesting to compare against X3D parts. I hope the pricing is sensible.
8 years is a good run. Not too short, but also not overly stretched out to absurd length of time.
Even if DDR6 comes with the next cycle (meaning roughly 2029 for both Intel and AMD) it's price will be high and it's performance lackluster compared to mature DDR5. This has happened with every memory generation. It's possible that DDR6 will come in 2031 instead of 2029.
That would make more sense.Lane count should increase. On that i agree.
But memory channel count need not increase. Consumer workloads dont benefit from triple or quad channel that much at it will only make everything more expensive. besides dual channel has no problem feeding 52 cores with data. AMD doubled core counts with Zen 2 and dual channel had no problem.
Intel going from 24c to 52c will be fine too as the memory speed support improves, too.The pricing will be high. Look at the amount of tiles and die space Intel will be using on the absolute cutting edge nodes.
Even if we look at mobile Panther Lake prices it sometimes approaches Strix Halo and that's with less silicon than Nova Lake and no bLLC.
This core count clusterfuck I just rather want to stay as far away from as I can. I don't see the need for all this overcomplication, all these bandaids, and all this lying through the teeth about power usage when in fact we're still looking at good old 'CORE' in a new coat.
Intel still needs that hard reset before I'm going to consider them again. Its just a matter of time before the next 14th gen blunder.
...as bad as the gap between the 5080 and 5090.
Pot, meet kettle.Wat? Consumer workloads benefit from more bandwidth. Please go look at core ultra reviews with CDO DIMMs. A wider bus would allow that without needing CDO DIMMs.
Meaningless in the grand scheme of things. CUDIMM has not managed to help Intel beat AMD.
Consumer workloads are not memory bandwidth limited.
Yeah, sensible.
4 different cpus inside. 3 different types of amd64 and npu6.
did the fix and improve the software for two different types of amd64 cores already over each software in every operating system? i doubt. I highly doubt three different amd64 cores are properly supported in these days software world. for pure server infrastructure without the need for real time it does not matter but for desktops i see possible issues.
intel should stick to standards. and the common name standard is usb 4. thunderbolt 5 implies most likely intel only and implies to research before purchase where are the differences etc.
this looks much more a headache for compatibility.
edit: i do not want to bother how to configure the compiler for those three different amd64 cpu core types. the npu hardly gets any use. last time i checked gcc there was no support for anything in this regards. no software support means you purchase stuff which is not in use.
If CUDIMM means you're getting less speed reduction and less latency increase with max RAM capacity compared to a mainstream performance baseline that means you're no longer choosing just the capacity when you have the need for it but you can also get enthusiast-ish specs on that huge RAM capacity config.
It's true that we're only talking a few percent here so it's mostly academic but why not? Progress is progress, at least it's an available option and people can choose it or not based on their budget.
"consumer workloads are not core limited" was the excuse when intel was making quad cores, now we've got 52 core consumer chips coming. Some of us would like our $1000+ purchases to not be restricted by memory bandwidth in the future. Hell look at the alder lake chips, when they launched everyone said the DDR5 was useless because there was no difference, bench them today and the DDR5 rig looks like a completely different generation of CPU.
Either way, the width of the bus does not determine if a consumer application can use it. All the application is worried about is if there is sufficient bandwidth.AMD tried that yet everyone sings their praises about how amazing they are, so /shrug
Now imagine a processor where, out of its 6 cores, only 2 reach the maximum advertised clock speed, only 2 have the advertised IPC, only two have the complete instruction set and only 2 have direct access to the L3 cache with low latency. Imagine a six-core processor where communication between some cores must go through some fabric that adds latency, which might even translate into microstuttering, both in games and applications. Imagine a hexa core CPU where Windows, in collaboration with the Intel Thread Director, must constantly decide where to send each thread, with all the latency issues this entails between the compute die and I/O die.
For me, though, if AMD decided tomorrow to sell me a 10-core Zen 6 processor with 2 Zen 6 cores, 2 Zen 5 cores, 2 Zen 4 cores, and 4 more Zen 3 cores , I would have a problem. I would feel like I've been deceived. You wouldn't. You would look at the 10 cores in task manager and say, "I have a 10-core Nova Lake processor".
Not everyone needs to agree with this, treating all cores as equal. But the more people who agree, the more companies will see it as consumer acceptance of this practice. And desktop processors will eventually become like mobile processors: one modern, fast core, and then, slower, less capable, but more cost-effective for the company to manufacture cores, selling as 6, 8, 10, 20, 50 core CPUs.
So, yes I prefer to call it "dual core" than "hexa core". Because I prefer a description that favors the consumer, not the company. If the company provides a clear description on the box, "2 high-speed high-performance cores and 4 low-power cores", that would of course be the most accurate. But until then, I prefer the "dual-core" description, which benefits the consumer by forcing the company to be more honest about what it's selling.What are you talking about? That was the normal for decades on Intel platforms.
The CPU has 6 cores. Calling it a hexa core CPU, meaning it has 6 cores, is not creative marketing. It is an objective fact.
Also WTF are you crying about clock speeds? Arrow lake has no issue with its E cores maintaining a consistent clock speed, as is written on the spec sheet. No misadvertising there. And the fabric thing? Do I even need to ask if you whined about AMD CPUs being called 8 cores when they had 2 quad core CCXs that used a fabric to communicate? Because if you didnt demand that the 2700x be labeled as a quad core for this same issue, then you are being a massive hypocrite.Not only does this not justify you demanding a 6 core be called a 2 core because you dont like the letter E, it doesnt make sense anyway, because the E and LPe cores used are NOT the same cores from alder lake. They are newer generations with more features and capabilities. Your analogy falls completely flat.
We've already had Zen 5 CPUs that use a mix of Zen 5 and 5c cores. Now, I'll ask again, did you complain about those? Mind showing where you demanded AMD only label them by their full zen 5 core count?The issue is not all the cores being treated as equal, its with you insisting that a core count be misrepresented because accurately naming the number of cores is "marketing tricks", which is objectively false doublespeak.Lying about core count doesnt benefit the consumer. It's also not accurate to label a hexa core CPU as a dual core. You are advocating lying about specs to make yourself feel better.Did you read my comment? Because it's pretty self explanatory. What part of my response to TFP is confusing to you? Did I ever say that intel didnt do that?