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Inquiry about validity of PCIe BAR mapping in PCI_MM_01 vs. PCI_MM_03 #282
Description
I am seeking clarification on the architectural assumptions behind the PCIe Memory Model tests, specifically comparing PCI_MM_01 (p045.c) and PCI_MM_03 (p094.c).
Observation
Upon reviewing the test implementations, there is a fundamental difference in how PCIe BAR space is mapped and accessed:
PCI_MM_01 (p045.c): Uses DEVICE_nGnRnE attributes to map the PCIe BAR(s) and validates aligned 32-bit accesses. This aligns with the standard architectural expectation for generic Device memory where side effects are unknown.
PCI_MM_03 (p094.c): Uses NORMAL_NC (Normal Non-Cacheable) attributes to map the PCIe BAR(s) and specifically checks for unaligned byte accesses.
The Concern
My understanding is that mapping a PCIe BAR as NORMAL_NC is only safe when the nature of the BAR is known beforehand (e.g., it is a linear framebuffer or a memory-like data buffer). In the context of a generic compliance test suite like BSA/SBSA ACS:
Attribute Mismatch: NORMAL_NC allows for gathering, reordering, and—critically—speculative reads. If a BAR contains "read-to-clear" registers or FIFO interfaces, mapping it as Normal memory can trigger unintended side effects that corrupt the device state.
Unaligned Accesses: While Normal memory supports unaligned accesses, many PCIe endpoints do not. Triggering an unaligned access to a device that expects strict alignment (often enforced by Device memory types) could result in an External Abort or undefined behavior.
Test Validity: Since the ACS does not have prior knowledge of the specific IP behind the BAR, why is NORMAL_NC considered a valid mapping for a generic test case?
Inquiry
What is the justification for using NORMAL_NC in PCI_MM_03 without knowing the endpoint's behavior?
Should this test be restricted only to certain classes of devices (e.g., those reporting as Prefetchable Memory in the PCI Configuration Space)?
Is there a risk that this test might cause false negatives (or system instability) on hardware that strictly adheres to Device memory semantics?
Your observations are valid. The behavior being tested depends on the nature of the BAR region being mapped, so the test should take into account what kind of memory or registers the BAR points to.
We will review this test and investigate how to make it more robust, including whether it should be restricted to specific BAR types or device classes.
We have made the respective changes and are verifying in multiple platforms, which is currently in progress to ensure its working fine. Would you want to take a look at the changes to run at your end and verify?
Activity
chetan-rathore commentedon Mar 20, 2026
Hi @tvidyasagar,
Thank you for the detailed analysis.
Your observations are valid. The behavior being tested depends on the nature of the BAR region being mapped, so the test should take into account what kind of memory or registers the BAR points to.
We will review this test and investigate how to make it more robust, including whether it should be restricted to specific BAR types or device classes.
Thanks,
Chetan
Rahulkunwar007 commentedon Apr 1, 2026
Hi @chetan-rathore ,
Any update on this?
Regards,
Rahul
chetan-rathore commentedon Apr 2, 2026
Hi @Rahulkunwar007,
The issue you raised is currently under investigation. We will share further updates as soon as they become available.
tvidyasagar commentedon Apr 10, 2026
Hi @chetan-rathore Thanks for looking into it.
May I know if there is any update here?
Sujana-M commentedon Apr 13, 2026
Hi @tvidyasagar,
We are currently discussing internally on the prospective changes. We will provide an update as soon as we conclude on it.
Thanks,
Sujana
tvidyasagar commentedon Apr 27, 2026
Hi @Sujana-M
Is there any update on this?
Sujana-M commentedon May 5, 2026
Hi @tvidyasagar,
We have made the respective changes and are verifying in multiple platforms, which is currently in progress to ensure its working fine. Would you want to take a look at the changes to run at your end and verify?
Thanks,
Sujana
tvidyasagar commentedon May 11, 2026
Sure... please share the patch and we are happy to verify and report back
Sujana-M commentedon May 12, 2026
Hi @tvidyasagar,
Please find the PR that has the changes #398
Thanks,
Sujana
fix(pcie): skip non-prefetchable BARs in P094 flow
Sujana-M commentedon May 18, 2026
Hi @tvidyasagar,
Please let us know if this fixes the issue at your end.
Thanks,
Sujana
tvidyasagar commentedon May 18, 2026
Sorry, we couldn't verify the fix.
I'll update on this before the end of this week.
Sujana-M commentedon Jun 1, 2026
Hi @tvidyasagar,
Please let us know if the issue is fixed at your end with this fix.
Thanks,
Sujana
tvidyasagar commentedon Jun 21, 2026
Apologies for the delay in reply. I can confirm that we no longer see the issue. Please proceed to merge the change and close the issue. Thanks.
Sujana-M commentedon Jun 22, 2026
Hi @tvidyasagar ,
Thank you for the confirmation, the PR has been merged.
Thanks,
Sujana