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Abstract
This paper presents the static random access memory (SRAM) precharge system by using an equaliser and a sense circuit. Recent goals of designing SRAM are to reduce area, delay, and power, and to maintain standard data stability and writability. By using an equaliser, column select and a sense circuit, precharging the bit-lines at Vdd-Vtp was successful. As charge is mostly shared during precharge and lower voltage swing occurs, dynamic power is lower. The performance of the proposed SRAM is analysed and compared with that of conventional SRAM. The write power of SRAM is reduced by 39.17% compared to conventional SRAM, when maintaining other parameters are almost the same.
Acknowledgements
The authors would like to thank the Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology (HKUST) for providing facilities and guidelines to conduct the research. Special thanks to Mr SM Salahuddin, Ph.D. candidate, Nanoelectronic Circuits and Gigascale Systems Laboratory, HKUST.
Notes on contributors
Mr Hussain Mohammed Dipu Kabir received a baccalaureate from the Department of Electrical and Electronics Engineering of Bangladesh University of Engineering & Technology in February 2011. He worked at Samsung Bangladesh R&D Centre as a Software/Sr Software Engineer from March 2011 to August 2013. Currently, he is a Ph.D. student of the HKUST, and is also an awardee of the Hong Kong Ph.D. Fellowship. His research interests are organic electronics, VLSI design, embedded system, MEMS and solid-state devices.
Mr Mansun Chan received his BS degree from the University of California (UC), San Diego in 1991, MS and Ph.D. degrees from the UC, Berkeley in 1994 and 1995, respectively. Since 1996, he has been in the Electrical and Electronic Engineering Faculty, the HKUST. He was a Visiting Professor with the UC at Berkeley and Co-director of the BSIM programme from July 2001 to December 2002. His research interests include nanodevice technologies, image sensors, SOI technologies, high-performance integrated circuits, 3D circuit technology, device modelling, and biomedical nano-electro-mechanical-systems technology.